Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
13
4.6. TPU Timer Status Register : TPUTST
The bit configuration of TPU timer status register is shown below.
TPUTST : Address 0910
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
TS[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
R,WX
This register indicates the operation status of each timer in TPU. This register is read only. Writing to the
register cause no influence in operation.
[bit7 to bit0] TS[7:0] (Timer Status) : Timer operation status
These bits indicate timer operation status of each channel.
Bit 0-7 corresponds to channel 0-7 respectively.
TSn
Operation Status
0
Ch.n Stop
1
Ch.n operate
(N = 0 to 7)
MB91520 Series
MN705-00010-1v0-E
2180