Fujitsu FR81S User Manual
CHAPTER 51: TIMING PROTECTION UNIT
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : TIMING PROTECTION UNIT
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.7. TPU Timer Interrupt Enable Register : TPUTIE
The bit configuration of TPU timer interrupt enable register is shown below.
TPUTIE : Address 0914
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
IE[7:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
This register is used to enable interrupt of each timer in TPU.
[bit7 to bit0] IE[7:0] (Interrupt Enable): Timer interrupt enable
These bits are used to set timer interrupt enable for each channel.
Bit 0-7 corresponds to channel 0-7 respectively.
IEn
Interrupt enable
0
Ch.n Interrupt disable
1
Ch.n Interrupt enable
(N = 0 to 7)
MB91520 Series
MN705-00010-1v0-E
2181