Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
29
4.11. PLL/SSCG Clock Selection Register : CCPSSELR
(CCtl Pll/Sscg clock Selection Register)
The bit configuration of the PLL/SSCG clock selection register is shown.
It is a register that selects the clock source supplied to system.
This register can be written only at PLL/SSCG clock oscillation stop (CSELR.PCEN = "0").
CCPSSELR: Address 0520
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
PCSEL
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
[bit7 to bit1] (Reserved)
[bit0] PCSEL (Pll Clock source Selection) : PLL/SSCG Clock source selection
It selects the PLL/SSCG clock source.
PCSEL
PLL or SSCG
0
Selects PLL
1
Selects SSCG
Note:
SSCG (Because it is unused) always becomes a reset status for PCSEL=0.
The PLL clock is supplied to CAN and OCDU for PCSEL=1.
MB91520 Series
MN705-00010-1v0-E
190