Fujitsu FR81S User Manual
APPENDIX
A. I/O Map
FUJITSU SEMICONDUCTOR LIMITED
APPENDIX
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
Address
Address offset value / Register name
Block
+0
+1
+2
+3
001818
H
SCR5/(IBCR5) [R/W]
B,H,W
0--00000
SMR5[R/W] B,H,W
000-00-0
SSR5[R/W] B,H,W
0-000011
ESCR5/(IBSR5)[R/W]
B,H,W
00000000
Multi-UART5
*1 Byte access is
possible only for
access to lower 8
bits.
*2 Reserved
because I
2
C mode
is not set
immediately after
reset.
*3 Reserved
because CSIO
mode is not set
immediately after
reset.
*4 Reserved
because LIN2.1
mode is not set
immediately after
reset.
00181C
H
― /(RDR15/(TDR15))[R/W] H,W
-------- -------- *3
RDR05/(TDR05)[R/W] B,H,W
-------0 00000000 *1
001820
H
SACSR5[R/W] B,H,W
0----000 00000000
STMR5[R] B,H,W
00000000 00000000
001824
H
STMCR5[R/W] B,H,W
00000000 00000000
― /(SCSCR5/SFUR5)[R/W] B,H,W
-------- -------- *3 *4
001828
H
― /(SCSTR35)/
(LAMSR5)
[R/W] B,H,W
-------- *3
― /(SCSTR25)/
(LAMCR5)
[R/W] B,H,W
-------- *3
― /(SCSTR15)/
(SFLR15)
[R/W] B,H,W
-------- *3
― /(SCSTR05)/
(SFLR05)
[R/W] B,H,W
-------- *3
00182C
H
―
― /(SCSFR25)
[R/W] B,H,W
-------- *3
― /(SCSFR15)
[R/W] B,H,W
-------- *3
― /(SCSFR05)
[R/W] B,H,W
-------- *3
001830
H
―/(TBYTE35)/
(LAMESR5)
[R/W] B,H,W
-------- *3
―/(TBYTE25)/
(LAMERT5)
[R/W] B,H,W
-------- *3
―/(TBYTE15)/
(LAMIER5)
[R/W] B,H,W
-------- *3
TBYTE05/(LAMRID5)
/
(LAMTID5)
[R/W] B,H,W
00000000
001834
H
BGR5[R/W] H, W
00000000 00000000
― /(ISMK5)[R/W]
B,H,W
-------- *2
― /(ISBA5)[R/W]
B,H,W
-------- *2
001838
H
FCR15[R/W]
B,H,W
---00100
FCR05[R/W]
B,H,W
-0000000
FBYTE5[R/W] B,H,W
00000000 00000000
00183C
H
FTICR5[R/W] B,H,W
00000000 00000000
―
―
MB91520 Series
MN705-00010-1v0-E
2247