Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
4.19. Clock Gear Configuration Setting Register 1 :
CCCGRCR1 (CCtl Clock Gear Config. Register 1)
The bit configuration of the clock gear configuration setting register 1 is shown.
Sets various settings of clock gear.
This register can be written only when PLL/SSCG clock oscillation is stopped (CSELR.PCEN = "0").
CCCGRCR1 : Address 052E
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
GRSTP[1:0]
GRSTN[5:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit7, bit6] GRSTP[1:0] (clock GeaR STeP selection) : Clock gear step selection
These bits select the step number at the time of clock gear up/down (the number of increment /decrement).
GRSTP[1:0]
Step number
00
1
01
2
10
3
11
4
[bit5 to bit0] GRSTN[5:0] (clock GeaR STart step Number selection) : Clock gear start step number
selection
These bits select the step at the start of clock gear operation and select the step between 0 and 63.
GRSTN[5:0]
Step number
000000
0
000001
1
000010
2
…
……
111101
61
111110
62
111111
63
Note:
The gear does not operate at GRSTN =111111(number 63 of steps) setting.
MB91520 Series
MN705-00010-1v0-E
201