Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
52
5.1.1. Main Clock (MCLK)
The main clock (MCLK) is shown.
The oscillation of the main clock stops on any of the following conditions.
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SINIT reset (See "CHAPTER: RESET")
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During the stop mode
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While the sub clock (SBCLK) are selected as the source clock and "0" is set to CSELR.MCEN
After all the above conditions of the oscillation stop are cancelled and then the oscillation stabilization wait
time which is set to CSTBR.MOSW[3:0] goes by, supplying the clock starts. The oscillation stabilization
wait time specified by the initial value is required because CSTBR.MOSW[3:0] is initialized at the time of
return from the reset input.
MB91520 Series
MN705-00010-1v0-E
213