Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
54
5.1.3. PLL/SSCG Clock (PLLSSCLK)
The PLL/SSCG clock (PLLSSCLK) is shown.
This LSI has PLL and SSCG (PLL which generates spread spectrum clock) and can select SSCG for reducing
noise. The combinations of clocks which CPU and peripheral functions can select are as follows.
Table 5-1 Clock Mode
Clock mode
RUN1
RUN2
RUN3
CPU
PLL
SSCG
SSCG
CAN
PLL
PLL
PLL
Peripheral
PLL
SSCG
PLL
OCDU
PLL
PLL
PLL
The CPU/Peripheral (timer/communication) clock is selected by CCPSSELR.PCSEL. Also, when CPU is
operated by the SSCG clock, peripheral (timer/communications) can be operated by the PLL clock. In this
case, the peripheral clock is selected by SACR.M and divided by PICD.PDIV[4:0].
Note:
When the CPU is operated by SSCG and the peripherals are operated by PLL, because the asynchronization
transfer enters between CPU/ Peripheral, the penalty of 5 ×PCLK2 to 8×PCLK2 is added to the access cycle.
In this case, the frequency of PCLK2 must be same as that of PCLK1. Select synchronization with SACR:M
when you want to make both CPU/Peripheral operation with the PLL clock.
The oscillation of the PLL/SSCG clock (PLLSSCLK) stops on any of the following conditions.
⋅
After the occurrence of reset (the bus idle wait time before stop is required. See "CHAPTER: RESET".)
⋅
While the main clock oscillation stops (PCEN=0)
⋅
During the time of main clock oscillation stabilization wait (PCEN=0)
⋅
During the watch mode
⋅
While a clock other than the PLL/SSCG clock (PLLSSCLK) are selected as the source clock and "0" is set
to CSELR.PCEN.
After all the above conditions of the oscillation stop are cancelled and then PLL/SSCG clock lock wait time
which is set to PLLCR.POSW[3:0] goes by, supplying the clock starts. The PLL/SSCG clock oscillation stops
until "1" is set to because CSELR.PCEN is initialized to "0" at the time of return from the reset input or the
INIT status.
MB91520 Series
MN705-00010-1v0-E
215