Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
66
Switches the source clock to the sub clock (CSELR.CKS[1:0]=01→11)
↓
While selecting the sub clock as the source clock (CMONR.CKM[1:0]=11)
4. the sub clock→the main clock divided by 2
While selecting the sub clock as the source clock (CMONR.CKM[1:0]=11)
↓
Sets the main clock oscillation stabilization wait time (sets CSTBR.MOSW[3:0])
– when the main oscillation is not enabled–
↓
Clears the main timer interrupt source (MTIF=0)
↓
(as necessary) Sets the main timer interrupt enable (MTIE=1)
↓
The main clock oscillation begins (MCEN=0→1)
↓
The main clock oscillation stabilization wait loop (loop until when MCRDY=1), or interrupt wait
↓
Clears the main timer interrupt (MTIF=0)
↓
Switches the source clock to the main clock divided by 2 (CSELR.CKS[1:0]=11→01)
↓
While selecting the main clock as the source clock (CMONR.CKM[1:0]=01)
↓
In a single clock product, returning the sub clock source setting
The sub clock oscillation stops (CSELR:SCEN=1→0)
↓
The CR clock is not selected as a sub-clock (CSVCR:SCKS=1→0)
MB91520 Series
MN705-00010-1v0-E
227