Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
68
Figure 5-5 Example of PLL/SSCG Mode Setting PLL/SSCG → Main
No
PLL/SSCG clock mode is confirmed.
Yes
The gear use is judged.
No
Yes
No
It is confirmed that the clock has high-speed stopped.
Yes
Gear start
No
The gear completion is confirmed.
Yes
Change to the main clock
No
Confirm whether the source clock has switched the main clock.
The operation of PLL/SSCG is stopped.
When PLL/SSCG clock exceeds 80MHz, FLASH access is set to no wait, again.
Dividing various clocks (CPU/Peripheral) is set.
When SSCG is used, peripheral resource is judged and whether it operates with PLL clock is judged.
When PLL is used, it is always synchronization.
No
Yes
The relation of the CPU/peripheral clock is set synchronously.
Start
CMONR.CKM=10
CSELR.CKS=10
Is the gear used?
CCCGRCR0.GRSTS=10
CCCGRCR0.GRSTR=1
CCCGRCR0.GRSTS=00
CSELR.CKS=00
CMONR.CKM=00
CSELR.PCEN=0
Main operation
DIVR2.DIVP
DIVR0.DIVB
Peripheral resource
Asynchronously ?
SACR.M=0
FCTLR.FAW
Yes
MB91520 Series
MN705-00010-1v0-E
229