Fujitsu FR81S User Manual
CHAPTER 7: RESET
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER :
RESET
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
5.4.2. Initialize Reset (INIT)
Initialize reset (INIT) is shown.
If a reset factor of the initialize reset (INIT) level occurs, an initialize reset (INIT) and a reset (RST) will be
issued at the same time. This reset is exclusively used for initializing the registers that cannot be initialized by
a reset (RST).
While this reset is being issued, all clocks become active. When this reset is issued, a reset (RST) will be
always issued at the same time. Although this reset initializes the clock control register, the oscillation of the
clock does not change while the main clock (MCLK) is oscillating.
If the main clock is inactive such as in a stop mode, it takes the main clock oscillation stabilization wait time.
Since the register of the clock control part will be initialized by a reset, the oscillation stabilization wait time
is the default value of this product (2
15
× main clock cycle).
Table 5-2
Oscillation Stabilization Wait Time
(INIT)
Is main clock oscillation
inactive before inputting
a reset?
Main clock oscillation stabilization wait time
No
None
Yes
2
15
× Main clock cycle
The following describes each reset issue sequence after reset factors of this reset have been released.
Figure 5-3 Initialize Reset (INIT) Sequence
INIT
Factor
RST
PCLK × 16 cycles
Additional oscillation stabilization wait time in the
event that main clock oscillation stabilization wait
time is required
PCLK × 4 cycles
*: PCLK × (1026+3) cycles
OCDU chip reset
sequence*
Because the clock settings register is initialized by reset, the period of the peripheral clock
(PCLK) is 8 times the period of the main clock (MCLK).
MB91520 Series
MN705-00010-1v0-E
290