Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
20
4.5. DMA Transfer Source Register 0 to 15 : DSAR0 to 15:
(DMA Source Address Register 0 to 15)
This section explains the bit configuration for DMA transfer source register 0 to 15.
These registers are 32-bit registers to indicate the transfer source address of each DMAC channel, and each
channel has these registers separately. This register must be accessed as a 32-bit data.
DSAR0 to 15: Address BASE + 0008
H
(Access: Word)
bit31
bit30
bit29
bit28
bit27
bit26
bit25
bit24
DSA[31:24]
Initial value
X
X
X
X
X
X
X
X
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit23
bit22
bit21
bit20
bit19
bit18
bit17
bit16
DSA[23:16]
Initial value
X
X
X
X
X
X
X
X
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
DSA[15:8]
Initial value
X
X
X
X
X
X
X
X
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
DSA[7:0]
Initial value
X
X
X
X
X
X
X
X
Attribute
R,W
R,W
R,W
R,W
R,W
R,W
R,W
R,W
[bit31 to bit0] DSA[31:0] (DMA Source Address) : DMA transfer source address
These registers indicate the transfer source address. If an increment or a decrement is set by DCCRn:SAC,
the address is updated according to the transfer size (DCCRn:TS). Also, the dedicated reload register is
provided. If DCCRn:SAR is "1", the value is returned to the initial value after data transfer.
Set a value in these registers not to cause a misalignment against the transfer size to be set by DCCRn:TS.
If the DMA transfer request source has a peripheral interrupt (DCCR:RS[1:0]=01), at least either the
transfer source address (DSAR) or the transfer destination address (DDAR) must be within the address
range of peripheral under control of 16-bit peripheral bus or 32-bit peripheral bus. For details, see "
Setting the ST Bit (Transfer source type) and DT Bit (Transfer destination type)".
MB91520 Series
MN705-00010-1v0-E
319