Fujitsu FR81S User Manual
FUJITSU SEMICONDUCTOR LIMITED
CONTENTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
4.1.1.
16-bit Dead Timer Register (TMRR) ................................................................................................... 2054
4.1.2.
16-bit Dead Timer State Control Register (DTSCR) ......................................................................... 2055
4.1.3.
16-bit Dead Timer Reload Interrupt Register (DTIR) ........................................................................ 2064
4.1.4.
16-bit Dead Timer Minus Control Register (DTMNS) ....................................................................... 2066
4.1.5.
Waveform Control Register 1/2 (SIGCR1, SIGCR2) ........................................................................ 2068
4.1.6.
PPG Output Control Register (PICS) .................................................................................................. 2071
5.
O
PERATION
............................................................................................................................... 2073
5.1.
Interrupts for Waveform Generator.................................................................................. 2074
5.2.
Operation of the Waveform Generator ............................................................................ 2075
6.
N
OTES
...................................................................................................................................... 2093
CHAPTER 49: BUS DIAGNOSIS FUNCTION ................................................................................. 2095
1.
O
VERVIEW
................................................................................................................................ 2096
2.
F
EATURES
................................................................................................................................. 2097
3.
C
ONFIGURATION
........................................................................................................................ 2098
4.
R
EGISTERS
............................................................................................................................... 2101
4.1.
Bus Diagnosis Status Register :BUSDIGSR ................................................................... 2102
4.2.
Bus Diagnosis Test Register :BUSTSTR0/1 ................................................................... 2105
4.3.
Bus Diagnosis Address Register :BUSADR ..................................................................... 2110
5.
O
PERATION
................................................................................................................................ 2112
5.1.
Error detection .................................................................................................................. 2113
5.2.
Test function ..................................................................................................................... 2115
5.3.
Notes ................................................................................................................................ 2116
5.4.
Example of operating bus diagnosis ................................................................................ 2117
CHAPTER 50: RAM DIAGNOSIS FUNCTION ................................................................................. 2123
1.
O
VERVIEW
................................................................................................................................ 2124
2.
F
EATURES
................................................................................................................................. 2125
3.
C
ONFIGURATION
........................................................................................................................ 2126
4.
R
EGISTERS
............................................................................................................................... 2128
4.1.
TEST Error Address Register 0 XBS RAM : TEAR0X .................................................... 2129
4.2.
TEST Error Address Register 1 XBS RAM : TEAR1X .................................................... 2131
4.3.
TEST Error Address Register 2 XBS RAM : TEAR2X .................................................... 2133
4.4.
TEST Start Address Register XBS RAM : TASARX ........................................................ 2135
4.5.
TEST End Address Register XBS RAM : TAEARX ......................................................... 2136
4.6.
TEST Diagnosis Function Register XBS RAM : TTCRX ................................................. 2137
4.7.
TEST Initialization Function Register XBS RAM : TICRX ............................................... 2140
4.8.
TEST Soft Reset Generation Control Register XBS RAM : TSRCRX ............................ 2142
4.9.
TEST Fake Error Generation Control Register XBS RAM : TFECRX............................. 2143
4.10.
TEST Key Code Control Register XBS RAM : TKCCRX ............................................. 2144
4.11.
TEST Error Address Register 0 BACKUP-RAM : TEAR0A ......................................... 2145
4.12.
TEST Error Address Register 1 BACKUP-RAM : TEAR1A ......................................... 2147
4.13.
TEST Error Address Register 2 BACKUP-RAM : TEAR2A ......................................... 2149
4.14.
TEST Start Address Register BACKUP-RAM : TASARA ............................................ 2151
4.15.
TEST End Address Register BACKUP-RAM : TAEARA ............................................. 2152
4.16.
TEST Diagnosis Function Register BACKUP-RAM : TTCRA ..................................... 2153
4.17.
TEST Initialization Function Register BACKUP-RAM : TICRA .................................... 2156
4.18.
TEST Soft Reset Generation Control Register BACKUP-RAM : TSRCRA ................. 2158
4.19.
TEST Fake Error Generation Control Register BACKUP-RAM : TFECRA ................. 2159
4.20.
TEST Key Code Control Register BACKUP-RAM : TKCCRA ..................................... 2160
5.
O
PERATION
............................................................................................................................... 2161
5.1.
Error detection ................................................................................................................. 2162
5.2.
RAM initialization operation ............................................................................................. 2163
5.3.
Interrupt-Related Register ............................................................................................... 2164
5.4.
RAM diagnosis fake error generation procedure ............................................................ 2165
5.5.
Number of Required Cycles ............................................................................................ 2166
5.6.
Note ................................................................................................................................. 2168
CHAPTER 51: TIMING PROTECTION UNIT ................................................................................... 2169
MB91520 Series
MN705-00010-1v0-E
(34)