Fujitsu FR81S User Manual
CHAPTER 8: DMA CONTROLLER (DMAC)
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : DMA CONTROLLER (DMAC)
FUJITSU SEMICONDUCTOR CONFIDENTIAL
28
5.1.2. Separate Items for Each Channel
This section explains the separate items for each channel of the DMA controller.
The following explains both the items to be set separately for each channel and the register setup procedure.
Register Setup Procedure
The channel registers must be set in the following procedure. When you set the DCCRn:CE bit to "1", be
sure to set the DTCRn to 1 or a higher value.
1. Clear the DCCRn:CE bit to disable the channel operation.
2. Clear each bit of DCSRn register to initialize the channel status flag.
3. Set the transfer source address (to be used when the transfer starts) in the DSARn register.
4. Set the transfer destination address (to be used when the transfer starts) in the DDARn register.
5. Set the transfer count in the DTCRn register. This count must be 1 or a larger value.
6. If transfer is started by a peripheral interrupt, the occurrence of each peripheral interrupt must be
enabled and the ICSEL and IORR registers must be set. (See the "CHAPTER: GENERATION AND
CLEARING OF DMA TRANSFER REQUESTS" about the ICSEL and IORR registers.)
7. Set the DCCRn register. During this time, the channel operation is enabled when the DCCRn:CE bit is
set.
Figure 5-1 Channel Register Setup Procedure
6. Settings for activation by interrupt
End settings
Start settings
1. Clear DCCRn:CE bit
3. Set DSARn
4. Set DDARn
5. Set DTCRn
7. Set DCCRn
2. Clear DCSRn to the initial state
MB91520 Series
MN705-00010-1v0-E
327