Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.5. DMA Request Clear Register 5 : ICSEL5 (Interrupt
Clear SELect register 5)
The bit configuration of DMA request clear register 5 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #39).
ICSEL5: Address 0405
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
SG_RX_SEL1[2:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
R/W
[bit2 to bit0] SG_RX_SEL1[2:0] (SG_RX SELection1) : Interrupt clear selection bits for sound
generator ch.1 / LIN-UART ch.7 transmission completion
SG_RX_SEL1[2:0]
Clear target
000
Reserved (Does not clear any)
001
Reserved (Does not clear any)
010
16-bit free-run timer 0 zero detection
011
16-bit free-run timer 0 compare clear
100
Multi-function serial ch.7 transmission completion
101 to 111
Reserved (Does not clear any)
Note:
Setting SG_RX_SEL1[2:0]= "000", "001" and "101" to "111" are prohibited. During this setting, no
interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
359