Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
21
4.12. DMA Request Clear Register 13 : ICSEL13 (Interrupt
Clear SELect register 13)
The bit configuration of DMA request clear register 13 is shown below.
These bits are used to select the peripheral that has generated the interrupt to be cleared (assigned to
interrupt vector number #52).
ICSEL13: Address 040D
H
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
ICUSEL0[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R0,WX
R/W
R/W
[bit1, bit0] ICUSEL0[1:0] : Interrupt clear selection for ICU ch.6
ICUSEL0[1:0]
Clear target
00
Reserved (Does not clear any)
01
32-bit ICU ch.6
10
Multi-function serial ch.10 reception completion
11
Reserved (Does not clear any)
Note:
Setting ICUSEL0[1:0]= "00" and "11" are prohibited. During this setting, no interrupt clear will be selected.
MB91520 Series
MN705-00010-1v0-E
366