Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
37
4.27. IO Transfer Request Setting Register 0 to 15 : IORR0
to 15 (IO triggered DMA Request Register for ch. 0 to
15)
15)
The bit configuration of IO transfer request setting register 0 to 15 is shown below.
If the DMA transfer request generation factor is specified as a peripheral interrupt request, these registers
are used to identify the vector number of the interrupt request that has generated the DMA transfer request.
An instance of these registers is provided for each DMA controller (DMAC) channel.
IORR0 to 15: Address 0490
H
to 049F
H
(Access: Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
Reserved
IOE
IOS[5:0]
Initial value
0
0
0
0
0
0
0
0
Attribute R0,W0
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit6] IOE (IO Enabled) : Transfer request enable bit
When an interrupt request specified by the IOS5 to IOS0 bits has been generated, this bit is used to notify
the DMA controller (DMAC) for the pertinent channel whether to output the DMA transfer request.
IOE
Function
0
No DMA transfer request output -- The interrupt request generated by the
peripheral is not used as a DMA transfer request (Initial value).
1
DMA transfer request output
[bit5 to bit0] IOS[5:0] (IO triggered DMA transfer request Select) : Transfer request selection bits
These registers are used to identify the interrupt request of the vector number that is used as the transfer
request source by the DMA controller (DMAC) for the channel corresponding to these registers.
IOS[5:0]
Interrupt vector number (Hexadecimal)
000000
0x10 (Initial value)
000001
0x11
000010
0x12
000011
0x13
000100
0x14
000101
0x15
:
:
101100
0x3C
101101
0x3D
101110
0x3E
101111
0x3F
11xxxx
Reserved
MB91520 Series
MN705-00010-1v0-E
382