Fujitsu FR81S User Manual
CHAPTER 9: GENERATION AND CLEARING OF DMA
TRANSFER REQUESTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: GENERATION AND CLEARING OF DMA TRANSFER REQUESTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
38
Note:
You cannot configure setting that causes interrupt requests with the same interrupt vector number to be
transfer requests from multiple DMA channels (example: simultaneous setting of IORR0 = 0x42 and
IORR1 = 0x42).
MB91520 Series
MN705-00010-1v0-E
383