Fujitsu FR81S User Manual
CHAPTER 11: I/O PORTS
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : I/O PORTS
FUJITSU SEMICONDUCTOR CONFIDENTIAL
9
4.1. Port Data Register 00 to 19 : PDR00 to 19 (Port Data
Register 00 to 19)
The bit configuration of port data register 00 to 19 is shown below.
These registers hold the output levels of the pins corresponding to individual ports that are in output mode.
PDR00 to PDR19 : Address 0000
H
, 0001
H
,
(Access : Byte, Half-word, Word)
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
P[7:0]
Initial
value
X
X
X
X
X
X
X
X
Attribute R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W R,RM/W
[bit7 to bit0] P (Port) : Port data setting bits
These bits set the output level of external pins P000, P001, ..., when the ports are in output mode.
PDR0.P[7:0] is for external pins P007 to P000
PDR1.P[7:0] is for external pins P017 to P010
PDR2.P[7:0] is for external pins P027 to P020
(A similar process continues)
The assignment is as shown above.
P[n]
Operation
0
Output of "0"
1
Output of "1"
The value read by a read-modify instruction is determined based on the combination with the data direction
register (DDR).
DDR
Reading by read-modify
instruction
PDR reading value
1
No
The PDR value can be read.
1
Yes
The PDR value can be read.
0
No
The pin value can be read.
0
Yes
The PDR value can be read.
PDR13.P7, PDR14.P[7:5, 1:0], PDR15.P[7:6] are reserved bits. Both writing to and reading from these bits
have no effect.
PDR13.P[6:5] are reserved bits in the dual clock products. Both writing to and reading from these bits have
no effect.
Some devices of the MB91520 series have ports missing. For details of which port is missing, see "1.16
Port function (General-Purpose I/O) Pins" in "CHAPTER:OVERVIEW". As for those bits allocated in the
missing ports, both writing and reading have no effect.
MB91520 Series
MN705-00010-1v0-E
404