Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
26
4.7. Timing Point Capture Value Setting Register : PTPC0
to PTPC47
The bit configuration of the Timing Point Capture value setting register is shown.
The Timing Point Capture value setting register (PTPC) sets interrupt and timing that generates the AD
activation trigger.
Timing Point Capture value setting register (PTPC): Address Base_addr + 0C
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
⋅
[bit15 to bit0] D15 to D0 : Timing Point Capture value setting bits
Interrupt and timing that generates the AD activation trigger is set.
Interrupt and AD activation trigger is generated according to the timing after (Timing Point Capture setting
value + 1 (*)) from the activation trigger. (*: When OWFS=0 is set)
Notes:
⋅
Be sure to set the register to become "Timing Point Capture setting value < PPG cycle setting value".
⋅
The value when the PPG output waveform selection bit (PCN.OWFS)="0" (Normal Wave Form) is
selected is set to the set Timing Point Capture value.
⋅
If the PPG output waveform selection bit (PCN.OWFS)=1 (Center Aligned Wave Form) is selected, a set
value of the Timing Point Capture value setting register is doubling (PCN.OWFS)="0".
⋅
Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the
value is not written at an upper and lower bit position.
MB91520 Series
MN705-00010-1v0-E
567