Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
24
[bit10] CMD : PPG communication mode enable bit
CMD
Explanation
0
PPG communication mode disable
1
PPG communucation mode enable
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
[bit9] TPC : Timing Point Capture enable bit
TPC
Explanation
0
Timing Point Capture mode disable
1
Timing Point Capture mode enable
[bit8] STRD : Start Delay mode enable bit
STRD
Explanation
0
Start Delay mode disable
1
Start Delay mode enable
[bit7 to bit3] Reserved bits
⋅
The reading value of these bits is always "0".
⋅
These bits must always be written to "0".
[bit2] REMP : PPG communication data register Empty flag bit
REMP
Explanation
0
no interrupt (state of Not Empty)
1
interrupt (state of Empty)
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
[bit1] SREMP : PPG communication data shift register Empty flag bit
SREMP
Explanation
0
no interrupt (state of Not Empty)
1
interrupt (state of Empty)
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
[bit0] IRS2 : Interrupt factor selection2 bit
IRS2 IRS1 IRS0
Explanation
0
0
0
STGR=0 : Software trigger or external trigger (TRG pin) input
STGR=1 : GATE signal trigger input
0
0
1
Borrow occurrence on the counter
0
1
0
Counter matched with the specified duty value
0
1
1
Borrow occurrence on the counter or counter matched with duty match
1
0
0
Timing Point Capture value match
Other value
PPG communication data register Empty factor
MB91520 Series
MN705-00010-1v0-E
565