Fujitsu FR81S User Manual
CHAPTER 17: PPG
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
4.12. PPG Communication Mode Data Setting Register :
PCMDDT0 to PCMDDT3
The bit configuration of the PPG communication mode data setting register is shown.
The PPG communication mode data setting register (PCMDDT) sets the control of the High/Low format
waveform output.
*: In PPG4 to PPG47, the communication function is not built into. The reading value of this bit is always
"0". This bit must always be written to "0".
PPG communication mode data setting register (PCMDDT): Address
Base_addr + 18
H
(Access: Half-word, Word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
D15
D14
D13
D12
D11
D10
D9
D8
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
D7
D6
D5
D4
D3
D2
D1
D0
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
[bit15 to bit0] D15 to D0 : PPG communication mode data setting bits
These bits control the PPG High/Low format waveform output.
When the register setting value is "1", the High format waveform is output. When the register setting value
is "0", the Low format waveform is output.
Note:
Be sure to access this register by the word (16-bit) format. If the byte is accessed to this register, the value is
not written at an upper and lower bit position.
MB91520 Series
MN705-00010-1v0-E
572