Fujitsu FR81S User Manual
CHAPTER 17: PPG
6. Notes
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: PPG
FUJITSU SEMICONDUCTOR CONFIDENTIAL
66
Cycle Value (PCSR) and Duty (PDUT) Settings
7. When writing a cycle value (PCSR) and a duty value (PDUT), be sure to observe the sequence of (1)
PCSR and (2) PDUT. Notes the following when rewriting the cycle value (PCSR) and duty value (PDUT):
(1) The cycle value (PCSR) and the duty value (PDUT) are fetched to the buffer when the duty value
(PDUT) is written and will be transferred from the buffer to the counter when an activation trigger is
generated or when a borrow occurs.
(2) If the cycle value (PCSR) or duty value (PDUT) is rewritten during the PPG operation, the new
value will be effective on the output waveform after the cycle next to the cycle after which the duty
value (PDUT) is written.
(3) If only the cycle value (PCSR) needs to be changed, (1) PCSR and (2) PDUT must be reconfigured
in that order. Then, the cycle value (PCSR) must be reset to the value that is equal to the duty value
(PDUT).
(4) The duty value (PDUT) may be freely rewritten.
8. The duty value (PDUT) must be equal to or smaller than the cycle value (PCSR). If the duty value is set
larger than the cycle value (PCSR), disable PPG operation before changing the duty value (PDUT) to a
smaller value. If PPG operation is not disabled, the following will occur:
(1) If the Normal Wave Form is selected (PCN.OWFS=0), the output level will be "H" or "L" depending
on the cycle value (PCSR)/duty value (PDUT) setting.
(2) If the Center Aligned Wave Form is selected (PCN.OWFS=1), the output level is always "L".
9. When accessing the cycle setting register (PCSR) and duty setting register (PDUT) of the PPG, be sure to
use word (16-bit) format. If these registers are accessed in byte format, the values are not written at an
upper and lower bit positions.
GATE Function
10. The GATE function control register (GATEC) is set before PPG activation.
Do not change the GATE selection bit (STGR) and the polarity selection bit (EDGE) of the GATE function
control register (GATEC) during the PPG operation.
11. It takes 4 clocks in internal clock until the PPG output is stopped after GATE signal is negated.
Others
13. If the interrupt request flag is set to "0" when interrupt request flag (PCN:IRQF) is "1", the flag clear
request is overwrited, and the interrupt request flag becomes "1".
14. The PPG cycle setting register (PCSR) and the PPG duty setting register (PDUT) are only for writing.
15. If the activation trigger selection bits (GTRS0 to GTRS11:TSELii[6:0]) are set to a value out of the
specifiable ranges (001_1000 to 001_1111, 010_0010 to 011_1111, and 101_1000 to 111_1111), once
disable PPG operation and write a correct value within specifiable ranges in order to restore the registers to
normalcy.
MB91520 Series
MN705-00010-1v0-E
607