Fujitsu FR81S User Manual
CHAPTER 18: WATCHDOG TIMER
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
5
2.1. Watchdog Timer 0 (Software Watchdog)
This section explains features of the watchdog timer 0.
⋅
Stop mode detection function
Able to detect the transition to watch mode or stop mode and generate a reset request
⋅
Watchdog timer clear
The timer is cleared by operation initialization reset or by writing the inverse value of the value
previously written to the clear register
⋅
Illegal write detection function
If the incorrect value is written to the clear register, a reset request is generated.
⋅
Watchdog timer period
The period can be selected from among sixteen choices of the peripheral clock (PCLK) × (2
9
to 2
24
)
cycles
⋅
Count stop conditions
The count stops while the CPU is stopped
⋅
To set the lower limit value of the timer count of the watchdog timer.
The value can be selected from among sixteen choices of the peripheral clock (PCLK) × (2
8
to 2
23
)
cycles.
⋅
Monitoring the watchdog timer window and generating a reset request.
If the clear register is written below the lower limit value of the timer count of the watchdog timer, the
watchdog timer generates a reset request.
MB91520 Series
MN705-00010-1v0-E
614