Fujitsu FR81S User Manual
CHAPTER 18: WATCHDOG TIMER
2. Features
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
6
2.2. Watchdog Timer 1 (Hardware Watchdog)
This section explains features of the watchdog timer 1.
This timer is driven by the clock generated by the built-in CR oscillator circuit immediately after the reset is
released. For information on settings (calibration) of the oscillator, see "CHAPTER: RTC/WDT1
(CALIBRATION)".
⋅
Watchdog timer clear
The timer is cleared by the operation initialization reset or by writing "0xA5" to the clear register.
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Illegal write detection function
If a value other than "0xA5" is written to the clear register, a reset request is generated
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Watchdog timer period
The period is fixed by the hardware at CR oscillator × 2
15
cycles
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Count stop conditions
The count stops when using ICE, during sleep mode, watch mode, stop mode, and when waiting for the
oscillator to stabilize when recovering from standby mode
MB91520 Series
MN705-00010-1v0-E
615