Fujitsu FR81S User Manual
CHAPTER 18: WATCHDOG TIMER
3. Configuration
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : WATCHDOG TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
7
3. Configuration
This section shows the configuration of the watchdog timer.
Figure 3-1 Block Diagram (Detailed)
WDTCPR0
CPAT
WDTCR0
RSTP
WDTCR0
WT
WDTCPR1
CPAT
WDTCR1
WT
PCLK
overflow
overflow
PCLK
CR oscillator
CR oscillator
CR oscillator
CMP
RST
RST
Stop/
Watch Mode
PCLK
EN
RST
EN
RST
WDT0 stops
WDT1 stops in sleep mode
and standby mode
PCLK
"0xa5"
Register value
CMP
Register value
Watchdog timer 0
Watchdog timer 1
Watchdog
reset 0
Watchdog
reset 1
Overflow
Overflow
R
S
Q
R
S
Q
maintained
in sleep mode
and standby mode
(24-bit up counter)
period selection
maintained
(24-bit up counter)
period selection
"0XA5"
Overflow
cycle select
ion
Overflow
cycle select
ion
clk_wdg1
Sleep mode
clk_wdg1
clk_wdg1
wdg1 en pin
Overflow
cycle compare
Overflow
cycle compare
Select
Select
MB91520 Series
MN705-00010-1v0-E
616