Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
14
4.1.2. Timer Control Registers 0, 1 : BTxTMCR (Base Timer
0/1 TiMer Control Register)
The bit configuration of timer control registers 0, 1 (BTxTMCR) is shown below.
These registers are used to variously configure and stop the base timer and to issue software triggers.
Notes:
⋅
If you need to change the FMD[2:0] setting, once reset it to FMD[2:0] = 000, and then set FMD[2:0] to
the desired value.
⋅
Reserved bits must be set to "0".
⋅
If you want to set bits of these registers except for the software trigger (STRG) bit, proceed as follows:
1. Once stop operation by writing FMD[2:0] = 000 or CTEN = 0.
2. Write desired values to the timer function selection bits (FMD[2:0]) and other bits.
⋅
When writing to the software trigger bit (STRG), be careful not to clear other bits.
⋅
Since FMD[2:0] = 000 specifies reset mode, you cannot set other bits when setting FMD[2:0] = 000.
⋅
These registers must be accessed in 16-bit mode.
⋅
These registers will also be initialized when reset mode is set (writing of BTxTMCR:FMD = 000).
BTxTMCR : Address Base_addr + 02
H
(Access: Half-word)
bit15
bit14
bit13
bit12
bit11
bit10
bit9
bit8
Reserved
CKS[2:0]
[PWM -
PPG]
RTGEN
[Others]
Reserved
[PWM -
PPG]
PMSK
[PWC]
EGS[2]
[Others]
Reserved
EGS[1:0]
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,WX(*3)
R/W
R/W
R/W
R/W
R0,WX(*1)
R/W
R0,WX(*1)
R/W
R/W
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
[Reload
timer -
PWC]
T32
[Others]
Reserved
FMD[2:0]
[Reload
timer - PWM
- PPG]
OSEL
[Others]
Reserved
MDSE
CTEN
STRG
Initial value
0
0
0
0
0
0
0
0
Attribute
R/W
R0,WX(*1)
R0,WX(*2)
R0,WX(*2)
R/W
R/W
R/W
R/W
R/W0(*1)
R/W
R/W
R0,W
(*1) Attribute assumed for "Reserved"
(*2) Attribute assumed for a 32-bit timer serving an odd-numbered channel
(*3) Attribute assumed for a 32-bit timer serving an odd-numbered channel or for a 16/32-bit PWC timer
MB91520 Series
MN705-00010-1v0-E
647