Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
PMSK
Description
0
Normal output
1
Fixed output
If the fixed output is selected by writing "1" to this bit, the level being output will vary depending on the
settings of the OSEL bit.
⋅
If OSEL=0 : "L" level will be output.
⋅
If OSEL=1 : "H" level will be output.
[Reload timer/PWM/PPG] [bit9, bit8] EGS[1:0] (EdGe Select) : Trigger input selection bits
Select an effective edge for the external activation trigger (TGIN) signal.
EGS[1:0]
Description
00
Trigger input has no effect on the operation
01
Rising edge
10
Falling edge
11
Both edges
[PWC] [bit10 to bit8] EGS[2:0] (EdGe Select) : Measurement mode selection bits
Select a measurement mode.
EGS[2:0]
Description
000
"H" pulse width measurement: Duration in which the input signal is maintained at
the "H" level
001
Rising edge interval measurement: Time from the detection of a rising edge to the
detection of the next rising edge
010
Falling edge interval measurement: Time from the detection of a falling edge to the
detection of the next falling edge
011
Edge-to-edge pulse width measurement: The width between consecutive input edges
is either:(1) or (2).
(1) Time from the detection of a rising edge to the detection of the falling edge
(2) Time from the detection of a falling edge to the detection of the rising edge
100
"L" pulse width measurement: Duration in which the input signal is maintained at
the "L" level(Time from the detection of a falling
edge to the detection of the rising edge)
101
110
111
Setting is prohibited
[Reload timer/PWC] [bit7] T32 (Timer 32bit) : 32-bit timer selection bit
MB91520 Series
MN705-00010-1v0-E
649