Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
32
4.4.2. L Width Setting Registers 0, 1 : BTxPRLL (Base Timer
0/1 Pulse Length of "L" register)
The bit configuration of L width setting registers 0, 1 (BTxPRLL) is shown below.
These registers set the default level for the signal output from the 16-bit PPG timer.
Notes:
⋅
These registers must be accessed in 16-bit mode.
⋅
Set these registers after selecting a base timer function to the PPG timer using the FMD2 to FMD0 bits
of the timer control register (BTxTMCR).
⋅
These registers will also be initialized when reset mode is set (writing of BTxTMCR:FMD = 000).
BTxPRLL : Address Base_addr + 08
H
(Access: Half-word)
bit15
bit14
- - -
bit2
bit1
bit0
D[15:0]
Initial value
0
0
- - -
0
0
0
Attribute R/W
R/W
- - -
R/W
R/W
R/W
[bit15 to bit0] D[15:0] (Data) : Data bits
These registers set the default level for the signal output from the 16-bit PPG timer. When the 16-bit down
counter completes counting down the value set to these registers, the level of the output waveform (TOUT)
will be inverted. Setting these registers and the base timer x H width setting reload register (BTxPRLH)
determines the widths of "L" level and "H" level for the output signal. The signal level width set to these
registers depends on the setting of the OSEL bit of the timer control register (BTxTMCR) as follows:
⋅
OSEL=0: "L" level width
⋅
OSEL=1: "H" level width
The value set to registers is loaded to the 16-bit down counter when a 16-bit PPG timer activation trigger is
detected or when the base timer x H width setting reload register (BTxPRLH) completed counting values and
underflows.
MB91520 Series
MN705-00010-1v0-E
665