Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
72
5.6.3. Operation in Reload Mode
This section explains the operation in reload mode.
This section explains the operation in reload mode.
Overview
In this mode, the values set in the base timer x L width setting reload register (BTxPRLL) and base timer x H
width setting reload register (BTxPRLH) are alternately reloaded to the down counter to ensure that the down
counter continues to count down. A desired pulse width can be output continuously by rewriting the base
timer x L width setting reload register (BTxPRLL) and base timer x H width setting reload register
(BTxPRLH) each time an underflow interrupt request is issued.
To use this mode, set reload mode by resetting the MDSE bit of the base timer x timer control register
(BTxTMCR) to "0"(MDSE=0).
Operation
Activation
Activate the 16-bit PPG timer with the following procedure:
1. Permit the 16-bit PPG timer operation by setting the CTEN bit of the timer control register
(BTxTMCR) to "1"(CTEN=1). The 16-bit PPG timer begins to wait for an activation trigger.
2. Enter an activation trigger by one of the following methods:
Set the STRG bit of the base timer x timer control register (BTxTMCR) to "1" (software trigger).
Enter an effective edge (an edge set in the EGS1 and EGS0 bits) for an external activation trigger
(TGIN signal).
Notes:
⋅
The external activation trigger (TGIN signal) entry method varies depending on the I/O mode specified
by the I/O selection register (BTSEL01).
⋅
After a 16-bit PPG timer activation trigger is detected, the following time is required before the value
(cycle) set in the L width setting reload register (BTxPRLL) can be loaded to the 16-bit down counter:
⋅
If a software trigger is input: 1T (T: Count clock cycle)
⋅
If an external event trigger is used: 2T to 3T (T:Count clock cycle)
Counting Operation
Counting operation initiated by the entry of an activation trigger is explained below, using an example where
the OSEL bit of the timer control register (BTxTMCR) is set for normal polarity (OSEL = 0).
1. The value set in the L width setting reload register (BTxPRLL) is transferred to the 16-bit down
counter and the value set in the base timer x H width setting reload register (BTxPRLH) is transferred
to the buffer. The 16-bit down counter begins to count down from the value of the L width setting
reload register (BTxPRLL). The output signal (TOUT) is at the "L" level.
2. The 16-bit down counter completes counting down from the value of L width setting reload register
(BTxPRLL).
3. The buffered value of H width setting reload register (BTxPRLH) is reloaded to the 16-bit down
counter, which continues counting down. The output signal (TOUT) is at the "H" level.
4. The 16-bit down counter completes counting down from the value of H width setting reload register
(BTxPRLH), thus causing an underflow.
5. The value of L width setting reload register (BTxPRLL) is reloaded to the 16-bit down counter, which
continues count down. The output signal (TOUT) is at the "L" level. In addition, the value of the H
width setting reload register (BTxPRLH) is transferred to the buffer.
6. Steps 2 to 5 are repeated to continue counting.
MB91520 Series
MN705-00010-1v0-E
705