Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
70
5.6.1. Overview
This section explains the overview of the 16-bit PPG timer operation.
The 16-bit PPG timer, once activated, decreases from the value initially specified by the base timer x L width
setting reload register (BTxPRLL). When counting down from the value set in the L width setting reload
register (BTxPRLL) is completed, the timer begins counting down from the value set in the H width setting
reload register (BTxPRLH).
When counting down from the value set in each register is completed, the output signal (TOUT) inverts its
level. Therefore, by configuring the L width setting reload register (BTxPRLL) and H width setting reload
register (BTxPRLH), you can arbitrarily set the widths of the "L" and "H" levels.
One of two 16-bit PPG timer operation modes can be selected using the MDSE bit of the timer control register
(BTxTMCR) as follows:
⋅
Reload mode (MDSE = 0): A sequence of "L"-level and "H"-level signals (consecutive pulses) is output.
⋅
One-shot mode (MDSE = 1): A string of one "L"-level signal and one "H"-level signal (single pulses) is
output.
MB91520 Series
MN705-00010-1v0-E
703