Fujitsu FR81S User Manual
CHAPTER 19: BASE TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: BASE TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
71
5.6.2. Pulse Width Calculation Method
This section explains the pulse width calculation method.
When the 16-bit PPG timer has counted down by the value set in the L width setting reload register
(BTxPRLL) or base timer x H width setting reload register (BTxPRLH) plus 1, the output signal (TOUT)
inverts its level. Therefore, the pulse width of the signal to be output is obtained by the following formula:
Example: If the output polarity is normal:
"L" level pulse width = T × (L + 1)
"H" level pulse width = T × (H + 1)
T: Count clock cycle
L: Value set in the base timer x L width setting reload register (BTxPRLL)
H: Value set in the base timer x H width setting reload register (BTxPRLH)
This means that when the L width setting reload register (BTxPRLL) and H width setting reload register
(BTxPRLH) are set to "0000
H
", the pulse width will be equal to one cycle of the count clock. When they are
set to "FFFF
H
", the pulse width will be equal to 65536 cycles of the count clock.
MB91520 Series
MN705-00010-1v0-E
704