Fujitsu FR81S User Manual
CHAPTER 23: 32-BIT INPUT CAPTURE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER
: 32-BIT INPUT CAPTURE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
16
5.1. Capture and Interrupt Timings
This section shows capture and interrupts timings.
Figure 5-1 Example of 32-Bit Input Capture Operation
(1) Rising edge of the input signal
(2) Internal signal generated by edge detection (synchronized to the peripheral clock)
(3) Free-run timer value is recorded to the capture register (capture).
(4) Input capture interrupt is generated (ICP(4 to 9)="1").
Interrupt request
FFFFFFFF
H
00000000
H
N
N+1
N+1
Enable free-run
timer operation
Count of
free-run
timer 3
Peripheral clock
(CLKP)
Input capture
Effective edge
N
N+1
Free-run timer 3
N+1
Capture register
Interrupt
request
Input capture
(1)
(2)
(3)
(4)
N
N+1
(1)
(2)
(3
(4)
MB91520 Series
MN705-00010-1v0-E
891