Fujitsu FR81S User Manual
CHAPTER 24: 16-BIT FREE-RUN TIMER
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : 16-BIT FREE-RUN TIMER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
40
5.2.3.
Compare Clear Buffer
The compare clear register (CPCLR) has a buffer function that can be enabled or disabled. When the buffer
function is enabled (BFE: bit23 of the TCCS register is 1), data written to the compare clear buffer register
(CPCLRB) will be transferred to the CPCLR register once the 16-bit free-run timer value "0" has been
detected. When the buffer function is disabled (BFE: bit23 of the TCCS register is 0), you will be able to
write data to the CPCLR register directly.
Figure 5-3 Operation in the Up Count Mode when the Compare Clear Buffer is Disabled
(BFE: bit23 of the TCCS register is 0)
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
Compare clear
buffer register
Compare clear
register
BFFF
H
Timer operation start
0 detection
Compare clear match
7FFF
H
FFFF
H
BFFF
H
7FFF
H
FFFF
H
Figure 5-4 Operation in the Up Count Mode when the Compare Clear Buffer is Enabled
(BFE: bit23 of the TCCS register is 1)
FFFF
H
BFFF
H
7FFF
H
3FFF
H
0000
H
Count value
Time
Compare clear
buffer register
Compare clear
register
BFFF
H
Timer operation start
0 detection
Compare clear match
7FFF
H
BFFF
H
7FFF
H
FFFF
H
FFFF
H
MB91520 Series
MN705-00010-1v0-E
947