Fujitsu FR81S User Manual
CHAPTER 27: UP/DOWN COUNTER
6. Operation and Setting Procedure Examples
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : UP/DOWN COUNTER
FUJITSU SEMICONDUCTOR CONFIDENTIAL
FUJITSU SEMICONDUCTOR CONFIDENTIAL
31
Count Operation
Normal operation
If the counter is operable and the rising or falling edge is input from the BIN pin, the input level of the AIN
pin is detected and the counter counts up or down.
pin is detected and the counter counts up or down.
Figure 6-6 shows the operation in the phase difference count mode (multiply-by-two).
Figure 6-6 Operation in the Phase Difference Count Mode (Multiply-by-two)
If, however, the ZIN pin is set as the gate function (CGSC=1) with the CGSC bit of the counter control
register (CCR), counting occurs only while the effective level set with the CGE1 and CGE0 bits is input
from the ZIN pin.
register (CCR), counting occurs only while the effective level set with the CGE1 and CGE0 bits is input
from the ZIN pin.
For information on effective level setting, see "4.3. Counter Control Register (CCR0, CCR1)".
Note:
The minimum pulse width required at the AIN, BIN, and ZIN pins is 2T (T is the cycle of the peripheral
clock (PCLK)).
clock (PCLK)).
Operation performed when the reload function is in use
The operation is similar to that in timer mode. See "
■ Counting" in "6.1. Operation in Timer Mode".
Operation performed when the compare function is in use
The operation is similar to that in up/down count mode. See "
■ Counting" in "6.2. Operation in Up/down
Count Mode".
Operation performed when the reload compare function is in use
The operation is similar to that in up/down count mode. See "
■ Counting" in "6.2. Operation in Up/down
Count Mode".
Checking Counting Direction
The operation is similar to that in the up/down count mode. See "
● Checking Counting Direction" in "6.2.
Operation in Up/down Count Mode".
AIN pin
Count value
BIN pin
+1
1
0
+1
2
+1
3
+1
4
+1
5
-1
4
+1
5
-1
4
-1
3
-1
2
-1
1
-1
0
MB91520 Series
MN705-00010-1v0-E
1038