Fujitsu FR81S User Manual
CHAPTER 36: EXTERNAL BUS INTERFACE
5. Operation
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : EXTERNAL BUS INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
35
5.7. Idle Cycle Insertion Function
This section shows the idle cycle insertion function.
Idle cycles can be inserted between accesses. The next access does not start during the idle cycle even if
there is a request, but starts after the idle cycle count finishes.
Figure 5-5 Idle Cycle Inserted
Read access idle cycles
If an access meeting any of the following conditions occurs in sequence after a read access, idle cycles are
inserted after the read access. This is configured using AWR:RIDL[1:0].
·
Write access
·
Access to another CS area
·
Access to a CS area configured with address/data multiplexed bus type
Note:
The only time when idle cycles are not inserted by RIDL is when sequential read accesses are performed on
the same CS area configured for split bus type.
Write recovery cycles
Idle cycles are inserted after a write access ends. This is configured using AWR:WRCV[1:0].
0
3
S
Y
S
CL
K
AS
X
CSnX
(n=0,1
,2,
3
)
Idle cycle
H: Dxx is input
L: Dxx is output
L: Dxx is output
MB91520 Series
MN705-00010-1v0-E
1234