Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
91
Writing "0" to this bit will reset it to "0".
SFD
Sync Field detection flag
0
No Sync Field detected
1
Sync Field detected
Notes:
⋅
When software reset is triggered (SCR:UPCL="1"), this bit will be reset to "0".
⋅
Writing "1" to this bit has no effect.
⋅
In both the master mode (SCR:MS="0") and the slave mode (SCR:MS="1"), this bit takes effect.
[bit12] SFDE: Sync Field detection interrupt enable bit
This bit is used to enable/disable Sync Field interrupts to the CPU.
When this bit is set to "1" and the Sync Field detection flag (SFD) is set to "1", a status interrupt request
will be output.
SFDE
Sync Field detection interrupt enable bit
0
Interrupts by Sync Field detection disabled
1
Interrupts by Sync Field detection enabled
[bit11] AUTE: Automatic baud rate adjustment bit
This bit is used to enable/disable automatic baud rate adjustment.
AUTE
Automatic baud rate adjustment bit
0
Automatic baud rate adjustment disabled
1
Automatic baud rate adjustment enabled
Notes:
⋅
In the master mode (SCR:MS="0"), this bit will be internally fixed to "0".
⋅
When this bit is set to "1", the timer operating clock division bit (TDIV3-0) will be set to "3h" (8
divisions).
⋅
This bit can be changed from "0" to "1" only when the serial timer enable bit (TMRE) is set to "0".
[bit10, bit9] TRG1-0: Trigger select bits
These bits are used to select how to detect an edge of an external trigger for activating the serial timer.
TRG1
TRG0
How to detect an edge of an external trigger
0
0
Falling edge detected
0
1
Rising edge detected
1
0
Both edges detected
1
1
Setting prohibited
Note:
These bits have no effect when the external trigger enable bit (TRGE) is set to "0".
MB91520 Series
MN705-00010-1v0-E
1404