Fujitsu FR81S User Manual
CHAPTER 40: MULTI-FUNCTION SERIAL INTERFACE
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : MULTI-FUNCTION SERIAL INTERFACE
FUJITSU SEMICONDUCTOR CONFIDENTIAL
130
4.5.5.
Serial Aid Control Status Register: SACSR
The serial aid control status register (SACSR) allows you to select how to activate the serial timer,
enable/disable timer interrupts, set the division value of the operating clock of the serial timer, and
enable/disable the serial timer.
SACSRn(n=3 to 8, 10, 11) : Address Base addr + 08
H
(Access: Byte, Half-word,
Word)
15
14
13
12
11
10
9
8
bit
-
-
-
-
-
TRG1
TRG0
TINT
0
0
0
0
0
0
0
0
Initial value
R/W
RX,WX RX,WX RX,WX RX,WX
R/W
R/W
R/W
Attribute
7
6
5
4
3
2
1
0
bit
TINTE
-
TRGE TDIV3 TDIV2 TDIV1 TDIV0 TMRE
0
0
0
0
0
0
0
0
Initial value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Attribute
[bit15 to bit11] Undefined
The read value is undefined. Writing has no effect on the operation.
[bit10, bit9] TRG1-0: Trigger select bits
These bits are used to select how to detect an edge of an external trigger for activating the serial timer.
TRG1
TRG0
How to detect an edge of an external trigger
0
0
Falling edge detected
0
1
Rising edge detected
1
0
Both edges detected
1
1
Setting prohibited
Note:
These bits have no effect when the external trigger enable bit (TRGE) is set to "0".
[bit8] TINT: Timer interrupt flag
When the serial timer register (STMR) matches the serial timer compare register (STMCR), the serial timer
register (STMR) will be set to "0", and this bit will be set to "1".
When this bit is set to "1" and the timer interrupt enable bit (TINTE) is set to "1", a status interrupt request
will be output.
Writing "0" to this bit will reset it to "0".
Writing "1" to this bit has no effect.
TINT
Description
0
No timer interrupt request
1
Timer interrupt request
Notes:
⋅
When software reset is triggered (SCR:UPCL="1"), this bit will be reset to "0".
⋅
For read-modify-write instructions, "1" will be read.
MB91520 Series
MN705-00010-1v0-E
1443