Fujitsu FR81S User Manual
CHAPTER 5: CLOCK
4. Registers
FUJITSU SEMICONDUCTOR LIMITED
CHAPTER : CLOCK
FUJITSU SEMICONDUCTOR CONFIDENTIAL
27
[bit3 to bit0] MOSW[3:0] (Main clock OSc Wait) : Main clock oscillation stabilization wait selection
The main timer interval is set by the set value for MOSW[3:0].
These bits select the oscillation stabilization wait time for the main clock (MCLK) as follows.
MOSW[3:0]
Main clock oscillation stabilization
wait time
At 4MHz
0000
2
15
×main clock cycle (Initial value)
8[ms]
0001
2
1
×main clock cycle
500[ns]
0010
2
5
×main clock cycle
8[μs]
0011
2
6
×main clock cycle
16[μs]
0100
2
7
×main clock cycle
32[μs]
0101
2
8
×main clock cycle
64[μs]
0110
2
9
×main clock cycle
128[μs]
0111
2
10
×main clock cycle
256[μs]
1000
2
11
×main clock cycle
512[μs]
1001
2
12
×main clock cycle
1[ms]
1010
2
13
×main clock cycle
2[ms]
1011
2
14
×main clock cycle
4[ms]
1100
2
17
×main clock cycle
33[ms]
1101
2
19
×main clock cycle
131[ms]
1110
2
21
×main clock cycle
524[ms]
1111
2
23
×main clock cycle
2[s]
Note:
Note that the determination detection is done while waiting for the oscillation stability when the cycle of the
determination detection is shorter than a set cycle of this register when the Clock supervisor function is
effective.
MB91520 Series
MN705-00010-1v0-E
188