Intel X3470 BV80605001905AJ User Manual

Datasheet, Volume 1

53

RESET_OBS#

This signal is an indication of the processor being reset.

O

Asynch 

CMOS

RSTIN#

Reset In: When asserted, this signal will asynchronously 

reset the processor logic. This signal is connected to the 

PLTRST# output of the PCH.

I

CMOS

RSVD

RESERVED. Must be left unconnected on the board. 

Intel does not recommend a test point on the board for 

this land.

RSVD_NCTF

RESERVED/Non-Critical to Function: Pin for package 

mechanical reliability. A test point may be placed on the 

board for this land. 

RSVD_TP

RESERVED-Test Point. A test point may be placed on the 

board for this land. 

SM_DRAMRST#

DDR3 DRAM Reset: Reset signal from processor to 

DRAM devices. One common to all channels. 

O

DDR3

PEG_ICOMPI

PCI Express Current Compensation.

I

Analog

PEG_ICOMPO

PCI Express Current Compensation.

I

Analog

PEG_RBIAS

PCI Express Resistor Bias Control.

I

Analog

PEG_RCOMPO

PCI Express Resistance Compensation.

I

Analog

PEG_RX[15:0]

PEG_RX#[15:0]

PCI Express Receive Differential Pair.

I

PCI 

Express

PEG_TX[15:0]

PEG_TX#[15:0]

PCI Express Transmit Differential Pair.

O

PCI 

Express

DMI_RX[3:0]

DMI_RX#[3:0]

DMI input from PCH: Direct Media Interface receive 

differential pair.

I

DMI

DMI_TX[3:0]

DMI_TX#[3:0]

DMI output to PCH: Direct Media Interface transmit 

differential pair.

O

DMI