Intel X3470 BV80605001905AJ User Manual

Datasheet, Volume 1

55

BPM#[7:0]

Breakpoint and Performance Monitor Signals: Outputs 

from the processor that indicate the status of 

breakpoints and programmable counters used for 

monitoring processor performance.

I/O

GTL

DBR#

DBR# is used only in systems where no debug port is 

implemented on the system board. DBR# is used by a 

debug port interposer so that an in-target probe can 

drive system reset.

O

PRDY#

PRDY# is a processor output used by debug tools to 

determine processor debug readiness.

O

Asynch 

GTL

PREQ#

PREQ# is used by debug tools to request debug 

operation of the processor.

I

Asynch 

GTL

TCK

TCK (Test Clock) provides the clock input for the 

processor Test Bus (also known as the Test Access Port).

I

TAP

TDI

TDI (Test Data In) transfers serial test data into the 

processor. TDI provides the serial input needed for JTAG 

specification support.

I

TAP

TDI_M

TDI_M (Test Data In) transfers serial test data into the 

processor. TDI_M provides the serial input needed for 

JTAG specification support.

I

TAP

TDO

TDO (Test Data Out) transfers serial test data out of the 

processor. TDO provides the serial output needed for 

JTAG specification support.

O

TAP

TDO_M

TDO_M (Test Data Out) transfers serial test data out of 

the processor. TDO_M provides the serial output needed 

for JTAG specification support.

O

TAP

TMS

TMS (Test Mode Select) is a JTAG specification support 

signal used by debug tools.

I

TAP

TRST#

TRST# (Test Reset) resets the Test Access Port (TAP) 

logic. TRST# must be driven low during power on Reset. 

I

TAP