Intel X3470 BV80605001905AJ User Manual

Product codes

BV80605001905AJ

Signal Description

Datasheet, Volume 1

6.6

PLL Signals

6.7

Intel

Flexible Display Interface Signals

Note:

The signals noted below as not being used are included for reference to define all LGA

1156 land locations. These signals will be used by future processors that are

compatible with LGA 1156 platforms.

Table 6-8.

PLL Signals

Signal Name

Description

Direction

Type

BCLK[0]

BCLK#[0]

Differential bus clock input to the processor.

Diff Clk

BCLK[1]

BCLK#[1]

Differential bus clock input to the processor. Reserved

for possible future use.

Diff Clk

BCLK_ITP

BCLK_ITP#

Buffered differential bus clock pair to ITP..

Diff Clk

PEG_CLK

PEG_CLK#

Differential PCI Express / DMI Clock In:
These pins receive a 100-MHz Serial Reference clock.

This clock is used to generate the clocks necessary for

the support of PCI Express. This also is the reference

clock for Intel

Flexible Display Interface.

Diff Clk

Table 6-9.

Intel

Flexible Display Interface

Signal Name

Description

Direction

Type

FDI_FSYNC[0]

Intel

Flexible Display Interface Frame Sync—Pipe A.