Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
109
1.9.6
CC - Class Code
B/D/F/Type: 0/2/0/PCI
Address Offset:
9-Bh
Default Value:
030000h
Access:
RO;
Size: 24
bits
This register contains the device programming interface information related to the
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
Sub-Class Code and Base Class Code definition for the IGD. This register also contains
the Base Class Code and the function sub-class in relation to the Base Class Code.
Bit Access Default
Value
Description
23:16 RO
03h
Base Class Code (BCC):
This is an 8-bit value that indicates the base
class code for the CPU Uncore. This code has
the value 03h, indicating a Display Controller.
This is an 8-bit value that indicates the base
class code for the CPU Uncore. This code has
the value 03h, indicating a Display Controller.
15:8 RO 00h
Sub-Class Code (SUBCC):
Value will be determined based on Device 0
GGC register, GMS and IVD fields.
00h: VGA compatible
80h: Non VGA (GMS = "0000" or IVD = "1")
Value will be determined based on Device 0
GGC register, GMS and IVD fields.
00h: VGA compatible
80h: Non VGA (GMS = "0000" or IVD = "1")
7:0 RO 00h
Programming Interface (PI):
00h: Hardwired as a Display controller.
1.9.7
CLS - Cache Line Size
B/D/F/Type: 0/2/0/PCI
Address Offset:
Ch
Default Value:
00h
Access:
RO;
Size: 8
bits
The IGD does not support this register as a PCI slave.
Bit Access Default
Value
Description
7:0 RO 00h
Cache Line Size (CLS):
This field is hardwired to 0s. The IGD as a PCI
compliant master does not use the Memory
Write and Invalidate command and, in general,
does not perform operations based on cache line
size.
This field is hardwired to 0s. The IGD as a PCI
compliant master does not use the Memory
Write and Invalidate command and, in general,
does not perform operations based on cache line
size.