Intel D425 AU80610006252AA User Manual

Datasheet 

 123 

B/D/F/Type: 0/2/0/PCI 

Address Offset: 

68-6Fh 

Default Value: 

0000000000000000h 

Access:  

W; 

Size: 64 

bits 

A CPU Dword/Qword write to this space flushes the Secondary CWB/DWB of all writes. 
The data is discarded. A CPU read to this space may result in a system hang. 

This register is for hardware debug purposes only. This is not relevant for software. 

All the data stored in the secondary CWB is flushed to memory before a write to this 
page is completed on the Front side bus.  The write data is discarded. 

All transactions from the CPU that follow are not processed by the chipset till the 
"flush write" completes creating a fence beyond which coherency is guaranteed.  

A read to this page does not flush the primary CWB/DWB and returns Zeros. 

 

 

63:0 W 

00000000
00000000

h 

Secondary CWB Flush Control (SCWBFC):  
A CPU Dword/Qword write to this space flushes 
the Secondary CWB/DWB of all writes. The data 
is discarded. A CPU read to this space may 
result in a system hang. 

B/D/F/Type: 0/2/0/PCI 

Address Offset: 

90-91h 

Default Value: 

D005h 

Access:  

RO; 

Size: 16 

bits 

When a device supports MSI it can generate an interrupt request to the processor by 

writing a predefined data item (a message) to a predefined memory address. The 
reporting of the existence of this capability can be disabled by setting MSICH (CAPL[0] 

@ 7Fh).  In that case walking this linked list will skip this capability and instead go 

directly to the PCI PM capability. 

 

15:8 RO  D0h 

Pointer to Next Capability (POINTNEXT):  
 This contains a pointer to the next item in the 
capabilities list which is the Power Management 
capability.

 

7:0 RO  05h 

Capability ID (CAPID):  
 Value of 05h identifies this linked list item 
(capability structure) as being for MSI registers.