Intel D425 AU80610006252AA User Manual
Product codes
AU80610006252AA
Processor Configuration Registers
Datasheet
69
1.6.3
C0DRB1 - Channel 0 DRAM Rank Boundary Address 1
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
202-203h
Default Value:
0000h
Access:
RW/L; RO;
Size: 16
bits
See C0DRB0
Bit Access Default
Value
RST/
PWR
Description
15:10 RO 000000b
Core
Reserved ()
9:0 RW/L 000h Core
Channel 0 Dram Rank Boundary Address 1
(C0DRBA1):
This register defines the DRAM rank boundary
for rank1 of Channel 0 (64 MB granularity)
=(R1 + R0)
(C0DRBA1):
This register defines the DRAM rank boundary
for rank1 of Channel 0 (64 MB granularity)
=(R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
1.6.4
C0DRB2 - Channel 0 DRAM Rank Boundary Address 2
B/D/F/Type: 0/0/0/MCHBAR
Address Offset:
Address Offset:
204-205h
Default Value:
0000h
Access:
RW/L; RO;
Size: 16
bits
See C0DRB0
Bit Access Default
Value
RST/
PWR
Description
15:10 RO 000000b
Core
Reserved ()
9:0 RW/L 000h Core
Channel 0 DRAM Rank Boundary Address 2
(C0DRBA2):
This register defines the DRAM rank boundary
for rank2 of Channel 0 (64 MB granularity)
=(R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB
(C0DRBA2):
This register defines the DRAM rank boundary
for rank2 of Channel 0 (64 MB granularity)
=(R2 + R1 + R0)
R0 = Total rank0 memory size/64MB
R1 = Total rank1 memory size/64MB
R2 = Total rank2 memory size/64MB
R3 = Total rank3 memory size/64MB