SMSC LAN9311 User Manual

Two Port 10/100 Managed Ethernet Switch with 16-Bit Non-PCI CPU Interface

Revision 1.4 (08-19-08)

256

SMSC LAN9311/LAN9311i

 

The reserved bits 31-16 are used to pad the register to 32-bits so that each register is on
a DWORD boundary. When accessed serially (through the MII management protocol), the
register is 16-bits wide.

The emulated link partner does not support next page, always instantly sends its link code
word, never sends a fault, and does not support 100BASE-T4.

The emulated link partner’s asymmetric/symmetric pause ability is based upon the values
of the 

 and 

 bits of the 

. Thus the emulated link partner always

accommodates the request of the Virtual PHY, as shown in 

. See 

 for additional information.

The emulated link partner always has the following capabilities: 100BASE-X full duplex,
100BASE-X half duplex, 10BASE-T full duplex, and 10BASE-T half duplex. For more
information on the Virtual PHY auto-negotiation, see 

.

7

100BASE-X Half Duplex
This bit indicates the emulated link partner PHY 100BASE-X half duplex 
capability.

RO

6

10BASE-T Full Duplex
This bit indicates the emulated link partner PHY 10BASE-T full duplex 
capability.

RO

5

10BASE-T Half Duplex
This bit indicates the emulated link partner PHY 10BASE-T half duplex 
capability.

RO

4:0

Selector Field
This field identifies the type of message being sent by Auto-Negotiation.

RO

00001b

No Flow Control Enabled

0

0

0

0

Symmetric Pause

1

0

1

0

Asymmetric Pause Towards 
Switch

0

1

1

1

Asymmetric Pause Towards MAC

1

1

0

1