Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Signal Descriptions
44
Datasheet, Volume 1
6.3
DMI2/PCI Express* Port 0 Signals
6.4
PECI Signal
6.5
System Reference Clock Signals
Table 6-6.
PCI Express* Miscellaneous Signals
Signal Name
Description
PE_RBIAS
This input is used to control PCI Express* bias currents. A 50 ohm 1%
tolerance resistor must be connected from this land to V
tolerance resistor must be connected from this land to V
SS
by the platform.
PE_RBIAS is required to be connected as if the link is being used even when
PCIe* is not used.
PCIe* is not used.
PE_RBIAS_SENSE
Provides dedicated bias resistor sensing to minimize the voltage drop caused
by packaging and platform effects. PE_RBIAS_SENSE is required to be
connected as if the link is being used even when PCIe* is not used.
by packaging and platform effects. PE_RBIAS_SENSE is required to be
connected as if the link is being used even when PCIe* is not used.
PE_VREF_CAP
PCI Express* voltage reference used to measure the actual output voltage
and comparing it to the assumed voltage. A 0.01 uF capacitor must be
connected from this land to V
and comparing it to the assumed voltage. A 0.01 uF capacitor must be
connected from this land to V
SS
.
Table 6-7.
DMI2 to Port 0 Signals
Signal Name
Description
DMI_RX_DN[3:0]
DMI_RX_DP[3:0]
DMI2 Receive Data Input
DMI_TX_DP[3:0]
DMI_TX_DN[3:0]
DMI2 Transmit Data Output
Table 6-8.
PECI Signals
Signal Name
Description
PECI
PECI (Platform Environment Control Interface) is the serial sideband interface
to the processor and is used primarily for thermal, power and error
management.
to the processor and is used primarily for thermal, power and error
management.
Table 6-9.
System Reference Clock (BCLK{0/1}) Signals
Signal Name
Description
BCLK{0/1}_D[N/P]
Reference Clock Differential input. These pins provide the PLL reference clock
differential input into the processor.
differential input into the processor.