Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Signal Descriptions
46
Datasheet, Volume 1
6.8
Processor Asynchronous Sideband and
Miscellaneous Signals
Miscellaneous Signals
Table 6-12. Processor Asynchronous Sideband Signals (Sheet 1 of 2)
Signal Name
Description
BIST_ENABLE
Input which allows the platform to enable or disable built-in self test (BIST) on the
processor. This signal is pulled up on the die; refer to
processor. This signal is pulled up on the die; refer to
Table 7-6
for details.
CAT_ERR_N
Indicates that the system has experienced a fatal or catastrophic error and cannot
continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine
check errors and other internal unrecoverable errors. It is expected that every
processor in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O
land, external agents are allowed to assert this land, which will cause the processor to
take a machine check exception. This signal is sampled after PWRGOOD assertion.
continue to operate. The processor will assert CAT_ERR_N for nonrecoverable machine
check errors and other internal unrecoverable errors. It is expected that every
processor in the system will wire-OR CAT_ERR_N for all processors. Since this is an I/O
land, external agents are allowed to assert this land, which will cause the processor to
take a machine check exception. This signal is sampled after PWRGOOD assertion.
On the processor, CAT_ERR_N is used for signaling the following types of errors:
•
Legacy MCERR’s, CAT_ERR_N is asserted for 16 BCLKs.
•
Legacy IERR’s, CAT_ERR_N remains asserted until warm or cold reset.
CPU_ONLY_RESET
Resets all the processors on the platform without resetting the DMI2 links.
ERROR_N[2:0]
Error status signals for integrated I/O (IIO) unit:
0 = Hardware correctable error (no operating system or firmware action necessary)
1 = Non-fatal error (operating system or firmware action required to contain and
recover)
2 = Fatal error (system reset likely required to recover)
MEM_HOT_C01_N
MEM_HOT_C23_N
Memory throttle control. MEM_HOT_C01_N and MEM_HOT_C23_N signals have two
modes of operation – input and output mode.
modes of operation – input and output mode.
Input mode is externally asserted and is used to detect external events such as
VR_HOT# from the memory voltage regulator and causes the processor to throttle the
appropriate memory channels.
VR_HOT# from the memory voltage regulator and causes the processor to throttle the
appropriate memory channels.
Output mode is asserted by the processor known as level mode. In level mode, the
output indicates that a particular branch of memory subsystem is hot.
output indicates that a particular branch of memory subsystem is hot.
MEM_HOT_C01_N is used for memory channels 0 & 1 while MEM_HOT_C23_N is used
for memory channels 2 & 3.
for memory channels 2 & 3.
PMSYNC
Power Management Sync. A sideband signal to communicate power management
status from the Platform Controller Hub (PCH) to the processor.
status from the Platform Controller Hub (PCH) to the processor.
PROCHOT_N
PROCHOT_N will go active when the processor temperature monitoring sensor detects
that the processor has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit has been activated, if enabled.
This signal can also be driven to the processor to activate the Thermal Control Circuit.
that the processor has reached its maximum safe operating temperature. This
indicates that the processor Thermal Control Circuit has been activated, if enabled.
This signal can also be driven to the processor to activate the Thermal Control Circuit.
This signal is sampled after PWRGOOD assertion.
If PROCHOT_N is asserted at the deassertion of RESET_N, the processor will tristate its
outputs.
outputs.
PWRGOOD
Power Good is a processor input. The processor requires this signal to be a clean
indication that BCLK, V
indication that BCLK, V
TTA
/V
TTD
, V
SA
, V
CCPLL
, V
CCD_01
and V
CCD_23
supplies are stable
and within their specifications.
“Clean” implies that the signal will remain low (capable of sinking leakage current),
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
without glitches, from the time that the power supplies are turned on until they come
within specification. The signal must then transition monotonically to a high state.
PWRGOOD can be driven inactive at any time, but clocks and power must again be
stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from
inactive to active when all supplies except V
stable before a subsequent rising edge of PWRGOOD. PWRGOOD transitions from
inactive to active when all supplies except V
CC
are stable. V
CC
has a VBOOT of zero
volts and is not included in PWRGOOD indication in this phase. However, for the active
to inactive transition, if any processor power supply (V
to inactive transition, if any processor power supply (V
CC
, V
TTA
/V
TTD
, V
SA
, V
CCD
, or
V
CCPLL
) is about to fail or is out of regulation, the PWRGOOD is to be negated.
The signal must be supplied to the processor; it is used to protect internal circuits
against voltage sequencing issues. It should be driven high throughout boundary scan
operation.
against voltage sequencing issues. It should be driven high throughout boundary scan
operation.
Note: V
CC
has a Vboot setting of 0.0 V and is not included in the PWRGOOD indication
and V
SA
has a Vboot setting of 0.9 V.