Intel 2760QM FF8062701065300 User Manual
Product codes
FF8062701065300
Datasheet, Volume 1
45
Signal Descriptions
6.6
JTAG and TAP Signals
6.7
Serial VID Interface (SVID) Signals
Table 6-10. JTAG and TAP Signals
Signal Name
Description
BPM_N[7:0]
Breakpoint and Performance Monitor Signals: I/O signals from the processor
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
that indicate the status of breakpoints and programmable counters used for
monitoring processor performance. These are 100 MHz signals.
EAR_N
External Alignment of Reset, used to bring the processor up into a deterministic
state. This signal is pulled up on the die; refer to
state. This signal is pulled up on the die; refer to
Table 7-6
for details.
PRDY_N
Probe Mode Ready is a processor output used by debug tools to determine
processor debug readiness.
processor debug readiness.
PREQ_N
Probe Mode Request is used by debug tools to request debug operation of the
processor.
processor.
TCK
TCK (Test Clock) provides the clock input for the processor Test Bus (also
known as the Test Access Port).
known as the Test Access Port).
TDI
TDI (Test Data In) transfers serial test data into the processor. TDI provides the
serial input needed for JTAG specification support.
serial input needed for JTAG specification support.
TDO
TDO (Test Data Out) transfers serial test data out of the processor. TDO
provides the serial output needed for JTAG specification support.
provides the serial output needed for JTAG specification support.
TMS
TMS (Test Mode Select) is a JTAG specification support signal used by debug
tools.
tools.
TRST_N
TRST_N (Test Reset) resets the Test Access Port (TAP) logic. TRST_N must be
driven low during power on Reset.
driven low during power on Reset.
Table 6-11. SVID Signals
Signal Name
Description
SVIDALERT_N
Serial VID alert.
SVIDCLK
Serial VID clock.
SVIDDATA
Serial VID data out.