Intel III 450 MHz 80525PY450512 Data Sheet
Product codes
80525PY450512
48
Datasheet
Signal Quality Specifications
3.3.1
Settling Limit Guideline
Settling limit defines the maximum amount of ringing at the receiving pin that a signal must reach
before its next transition. The amount allowed is 10 percent of the total signal swing (V
before its next transition. The amount allowed is 10 percent of the total signal swing (V
HI
– V
LO
)
above and below its final value. A signal should be within the settling limits of its final value, when
either in its high state or low state, before it transitions again.
either in its high state or low state, before it transitions again.
Signals that are not within their settling limit before transitioning are at risk of unwanted
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
oscillations which could jeopardize signal integrity. Simulations to verify settling limit may be
done either with or without the input protection diodes present. Violation of the settling limit
guideline is acceptable if simulations of 5 to 10 successive transitions do not show the amplitude of
the ringing increasing in the subsequent transitions.
Figure 16. Low to High AGTL+ and Non-AGTL+ Receiver Ringback Tolerance
Figure 17. Signal Overshoot/Undershoot, Settling Limit, and Ringback
0.7V Clk Ref
Clock
Time
V
start
V
REF
- 0.2
V
REF
V
REF
+ 0.2
Note: High to low case is analogous
τ
α
δ
ρ
φ
Undershoot
Overshoot
Settling Limit
Settling Limit
Rising-Edge
Ringback
Ringback
Falling-Edge
Ringback
Ringback
V
LO
V
SS
Time
000767
V
HI