Intel E7-8891 v2 CM8063601377422 User Manual

Product codes
CM8063601377422
Page of 504
Processor Uncore Configuration Registers
106
Intel
®
 Xeon
® 
Processor E7-2800/4800/8800 v2 Product Family
Datasheet Volume Two: Functional Description, February 2014
13.2.1.17 SMBCNTL_[0:1]
SMBus Control.
30:30
RWS
0x0
SMB_PNTR_SEL (smb_pntr_sel):
Pointer Selection: SMBus/I2C present pointer based access enable when set; 
otherwise, use random access protocol. Hardware based TSOD polling will also 
use this bit to enable the pointer word read.
Important Note: Cpu hardware based TSOD polling can be configured with 
pointer based access. If software manually issue SMBus transaction to other 
address, i.e. changing the pointer in the slave device, it is software's 
responsibility to restore the pointer in each TSOD before returning to hardware 
based TSOD polling while keeping the SMB_PNTR_SEL = 1.
29:29
RWS
0x0
SMB_WORD_ACCESS (smb_word_access):
Word access: SMBus/I2C word (2B) access when set; otherwise, it is a 
byte access.
28:28
RWS
0x0
SMB_WRT_PNTR (smb_wrt_pntr):
Bit[28:27] = 00: SMBus Read
Bit[28:27] = 01: SMBus Write
Bit[28:27] = 10: illegal combination
Bit[28:27] = 11: Write to pointer register SMBus/I2C pointer update (byte). bit 
30, and 29 are ignored. Note: SMBCntl_[0:1] [26] will NOT disable WrtPntr 
update command.
27:27
RWS
0x0
SMB_WRT_CMD (smb_wrt_cmd):
When '0', it's a read command
When '1', it's a write command
26:24
RWS
0x0
SMB_SA (smb_sa):
Slave Address: This field identifies the DIMM SPD/TSOD to be accessed.
23:16
RWS
0x0
SMB_BA (smb_ba):
Bus Txn Address: This field identifies the bus transaction address to be 
accessed.
Note: in WORD access, 23:16 specifies 2B access address. In Byte access, 
23:16 specified 1B access address.
15:0
RWS
0x0
SMB_WDATA (smb_wdata):
Write Data: Holds data to be written by SPDW commands.
Since TSOD/EEPROM are I2C devices and the byte order is MSByte first in a 
word write, writing of I2C using word write should use SMB_WDATA[15:8] = 
I2C_MSB and SMB_WDATA[7:0] = I2C_LSB. If writing of I2C using byte write, 
the SMB_WDATA[15:8] = don’t care; SMB_WDATA[7:0] = write_byte.
If we have a SMB slave connected on the bus, writing of the SMBus slave using 
word write should use SMB_WDATA[15:8] = SMB_LSB and SMB_WDATA[7:0] 
= SMB_MSB.
It is software responsibility to figure out the byte order of the slave access.
Type:
CFG
PortID: N/A
Bus:
1
Device: 15
Function:
0
Bus:
1
Device: 29
Function:
0
Offset:
0x184, 0x194
Bit
Attr
Default
Description
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